/*
* Userland sanbox of the OCP-TAP time card driver
*/
#include <u.h>
#include <libc.h>
#include <bio.h>
#include "pci.h"
//#define csr32r(c, r) (*((c)->io+((r)/4)))
//#define csr32w(c, r, v) (*((c)->io+((r)/4)) = (v))
#define csr32r(c, r) (*((c)+((r)/4)))
#define csr32w(c, r, v) (*((c)+((r)/4)) = (v))
enum {
/* ptm_reg */
PtmCtl= 0,
PtmStat= 1,
PhyTxDy= 2,
PhyRxDy= 3,
MTime0= 4,
MTime1= 5,
LinkDy= 6,
T1Time0= 7,
T1Time1= 8,
T4Time0= 9,
T4Time1= 10,
};
enum {
/* ocp_reg */
OcpCtl= 0,
OcpStat= 1,
OcpSel= 2,
OcpVer= 3,
OcpNsec= 4,
OcpSec= 5,
AdjNsec= 8,
AdjSec= 9,
DriftNsec= 12,
DrWinNsec= 13,
ServoOffP= 20,
ServoOffI= 21,
ServoDriftP= 22,
ServoDriftI= 23,
OcpStatOff= 24,
OcpStatDrift= 35,
};
enum {
OcpCtlEn= 1<<0,
OcpCtlAdjT= 1<<1,
OcpCtlAdjO= 1<<2,
OcpCtlAdjDr= 1<<3,
OcpCtlAdjSv= 1<<8,
OcpCtlRdTimeRq= 1<<30,
OcpCtlRdTimeOk= 1<<31,
};
enum {
OcpSelClkNone= 0,
OcpSelClkReg= 0xfe,
};
enum {
/* tod_reg */
TodCtl= 0,
TodStat= 1,
TodSioPol= 2,
TodVer= 3,
TodAdjSec= 4,
TodSioBaud= 8,
UtcStat= 12,
UtcLeap= 13,
GnssStat= 16,
GnssNsat= 17,
};
enum {
TodCtlEn= 1<<0,
TodCtlDisFA= 1<<17,
TodCtlDisFB= 1<<18,
};
enum {
/* ts_reg */
TsEn= 0,
TsErr= 1,
TsPol= 2,
TsVer= 3,
TsCabDy= 8,
TsIntr= 12,
TsIntrM= 13,
TsCount= 15,
TsNsec= 16,
TsSec= 17,
TsDatW= 18,
TsDat= 19,
};
enum {
/* pps_reg */
PpsCtl= 0,
PpsStat= 1,
PpsCabDy= 8,
};
enum {
/* img_reg */
ImgVer= 0,
/* msi_reg */
MsiEn= 0,
/* gpio_reg */
Gpio1= 0,
Gpio2= 2,
/* frequency_reg */
FrCtl= 0,
FrStat= 1,
/* board_config_reg */
BcrMro50En= 0,
};
enum {
/* dcf_master_reg, dcf_slave_reg */
DrCtl= 0,
DrStat= 1,
DrVer= 3,
DrAdjSec= 4,
};
enum {
/* signal_reg */
SigEn= 0,
SigStat= 1,
SigPol= 2,
SigVer= 3,
SigCabDy= 8,
SigIntr= 12,
SigIntrM= 13,
SigStartNsec= 16,
SigStartSec= 17,
SigPulseNsec= 18,
SigPulseSec= 19,
SigPeriodNsec= 20,
SigPeriodSec= 21,
SigRptCount= 22,
};
enum {
/* irig_master_reg, irig_slave_reg */
IrCtl= 0,
IrStat= 1,
IrVer= 3,
IrAdjSec= 4,
IrModCtl= 5,
};
enum {
/* ptp_ocp_eeprom_map */
EepromFBSerialMac= 0,
EepromFBBoardID= 0x43,
EepromArtSerialMac= 0x200,
EepromArtBoardID= 0x243,
};
enum {
/* ocp_fb_resource_rev1 */
ImgBase= 0x00020000,
ExtBase= 0x00100000,
PPSSEL= 0x00130000,
SmaMap1= 0x00140000,
I2CBase= 0x00150000,
SioGnssBase= 0x00161000,
SioGnss2Base= 0x00171000,
SioMacBase= 0x00181000,
SioNmeaBase= 0x00191000,
SmaMap2= 0x00220000,
SpiFlashBase= 0x00310000,
MacBase= 0x00181000,
MemBase= 0x01000000,
Ts0Base= 0x01010000,
Ts1Base= 0x01020000,
PPS2EXT= 0x01030000,
PPS2CLK= 0x01040000,
TOD= 0x01050000,
Ts2Base= 0x01060000,
IrigIn= 0x01070000,
IrigOut= 0x01080000,
DcfIn= 0x01090000,
DcfOut= 0x010A0000,
NmeaOut= 0x010B0000,
PpsBase= 0x010C0000,
Sig0Base= 0x010D0000,
Sig1Base= 0x010E0000,
Sig2Base= 0x010F0000,
Sig3Base= 0x01100000,
Ts3Base= 0x01110000,
Ts4Base= 0x01120000,
FreqIn0= 0x01200000,
FreqIn1= 0x01210000,
FreqIn2= 0x01220000,
FreqIn3= 0x01230000,
};
enum {
/* ocp_fb_resource_rev2 */
MsiBase= 0x1800, /* CSR_PCIE_MSI_BASE */
PrqBase= 0x3000, /* CSR_PTM_REQUESTER_BASE */
};
struct Flash {
/* ptp_ocp_flash_info */
char* name;
int pcioff;
int nb;
uchar* b;
};
struct FirmwareHdr {
/* ptp_ocp_firmware_header */
char magic[4]; /* "OCPC" */
ushort vid;
ushort did;
ulong len;
ushort rev;
ushort crc;
};
static void
reset(void)
{
Pcidev *p;
ulong *mmio;
ulong v;
p = pcimatch(0, 0x1ad7, 0xa000);
if(p == nil) {
print("ocptap: device not found\n");
return;
}
if(p->mem[0].bar == 0){
print("ocp timecard driver needs a patch to pci.c:/pciscan (add case 0xFF)\n");
return;
}
print("ocptap: timecard detected:");
pcihinv(p);
Bflush(&stdout);
mmio = segattach(0, "ocptap.mmio", 0, p->mem[0].size);
if(mmio == (void*)-1){
print("%s: can't attach mmio segment\n", "ocptap");
return;
}
print("ocptap: mmio mapped\n");
v = csr32r(mmio, MemBase);
print("MemBase\t%.8lux: %.8lux\n", (ulong)MemBase, v);
print("ocptap: .\n");
}
void
ocptaplink(void)
{
reset();
}
void
main(int, char**)
{
fmtinstall('H', encodefmt);
Binit(&stdout, 1, OWRITE);
reset();
exits("");
}
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